Ferranti Argus

Ferranti's Argus computers were a line of industrial control computers offered from the 1960s into the 1980s. They were widely used in a variety of roles in Europe, particularly in the UK where they continue to serve as monitoring and control systems for nuclear reactors.

Contents

Original series

The original Argus was developed in 1958 as a ground-based control computer for the Bristol Bloodhound Mark 2 missile. The Bloodhound had a radar dish in the nose of the missile that had to be locked down during launch due to the vibration of the solid fuel rocket boosters that got the missile up to speed. Once the boosters were burned out and ejected, the radar antenna would be unlocked and start tracking the target. The Argus calculated where the target would be relative to the missile at the point of burnout, feeding that to the missile before launch and thereby allowing it to slew the radar to the correct angle. Although originally designed solely for military use, the Argus was later selected to control the operation of an ammonia/soda plant by ICI at their Fleetwood operations in 1962.[1]

The Argus circuitry was based on germanium transistors with 0 and -6 volts representing binary 1 and 0, respectively. The computer was based on a 12-bit word length with 24-bit instructions. The arithmetic was handled in two parallel 6-bit ALUs operating at 500 kHz. Additions in the ALU took 12 µs, but adding in the memory access time meant simple instructions took about 20 µs. Double-length (24-bit) arithmetic operations were also provided. Data memory was supplied in a 12-bit, 4096 word, core memory store, while up to 64 instruction words were stored in a separate plugboard array, using ferrite pegs dropped into holes to create a "1". Op codes were 6 bits, registers 3 bits, index register (modifier) 2 bits and data address 13 bits.

The original design was followed in 1963 by the single-ALU Argus 100, which was also intended for process control use. Unlike the original, the Argus 100 used a flat 24-bit addressing scheme with both data and code stored in a single memory. Only a 5-bit opcode was used in order to simplify the basic logic and gain an address bit. The single ALU and other changes resulted in a basic operation time of 72 μs. One notable use of the Argus 100 was to control the Jodrell Bank Mark II telescope in 1964. With the 100's release, the original design was renamed Argus 200 as it was considered more powerful.

The design of the Argus 300 was started in 1963 as a much faster machine featuring a fully parallel-architecture arithmetic logic unit, as opposed to the earlier and much slower serial units. Its instruction set was nevertheless fully compatible with the Argus 100. The 300 was very successful and used throughout the 1960s in various industrial roles. There was a variant of the 300, the Argus 350, which allowed external access to its core to allow direct memory access. This improved performance of input/output, avoiding having to move data via code running on the processor. The 350 was used in various military simulators, including the Royal Navy for frigate, submarine and helicopter based anti-submarine training, and the Royal Air Force for a Bloodhound Mk.II simulator and the Vickers VC10 Flight Simulator built at Redifon and delivered to RAF Brize Norton in 1967. The actual computer used on the VC10 Simulator was a 3520B, this meant that it had (20)kWords of memory and a (B)acking Store. The 350's were delivered in the 1967 to 1969 timeframe.

Silicon replacements

The design of the Argus 400 started at the same time as the Argus 300. In logical terms the 400 was similar to the earlier 100, using serial ALUs. However, it featured an entirely new electrical system. Previous machines used germanium transistors to form the logic gates. The Argus 400 used silicon transistors in a NOR-logic designed by Ferranti Wythenshawe called MicroNOR II, with more "conventional" logic where 0 and +4.5 represented binary 1 and 0, respectively. The rest of the world however used 0 volts to represent 0 and + 2.4 (to 5) volts to represent 1. This was called NAND logic. They are in fact both the same circuitry. When Texas Instruments brought out their “74” series of integrated circuits the specification of MicroNOR II was changed from 4.5 volts to 5 volts so the two families could work together. The machine was packaged to fit into a standard A.T.R. aircraft case. Multilayer PCBs were not routine in 1963 and Ferranti developed processes for bonding the boards and plating through the circuit boards. The drawing office had to learn how to design multilayer boards (tape onto film in those days). It took around two years for the Argus 400 to go into production.

The Argus 500, designed about 3 years later, used parallel arithmetic and was much faster. It was designed to be plugged into a larger 19 inch rack mounted frame, together with up to four core store (memory) units. The Argus 400 was repackaged to be the same as the Argus 500 and the two machines were plug compatible. The Argus 400 used 18 small PCBs for its CPU each of which was wire-wrapped to the backplane using 70 miniature wire wraps. Removing a card was tedious. The Argus 500 initially used the same packages, and also wire-wrap, on larger boards, but later versions employed dual-in-line ICs which were soldered flat onto the PCB and were much easier to remove.

Like the earlier designs, the 400 and 500 used the same 14-bit address space and 24-bit instruction set and were compatible. The 500 added new instructions that used three-bits of the accumulator for offset indexing as well. Both machines ran at a 4 MHz basic clock cycle, much faster than the earlier machines' 500 kHz. Both used core memory which was available in two cycle times, The Argus 400 used a 2 μs core whereas the Argus 500 had 2 μs in earlier machines and 1 μs for later ones, doubling performance. The difference between the 400 and 500 was similar to the split between the 100 and 300, in that the 500 had a parallel ALU and the 400 was serial. The Argus 400 had an add time (two 24 bit numbers of 12 μs. The Argus 500 (with 1 μs store) took 3 μs. Divide (the longest instruction) took 156 μs on the Argus 400 and the Argus 500 took 9 μs. The Argus 500 was of course much more expensive. Typical Argus 500 installations were chemical plants (process control) and nuclear power stations (process monitoring). A later application was for Police Command and Control installations, one of the more famous ones being for Strathclyde Police in Glasgow. This system provided the first visual display of resource locations using maps provided by 35mm slide projectors projecting through a port-hole in the tube of the VDU screen.

An Argus 400 replaced the 100 at Jodrell Bank in 1971.[2] There was a special version of the Argus 400 made for the Boadicea seat booking network for BOAC. This removed the multiply and divide functions as these used a significant number of expensive JK flip-flops and it was cost effective at the time to save these 24 and a few other components.

ASCII-based designs

Breaking with the past, the next series of Argus machines were completely new designs and not backward compatible. The Argus 600 was an 8-bit machine, and this was followed by the Argus 700 which used 16-bit architecture. Design of the 700 started around 1968/9 and the range was still in production in the mid 1980s achieving international success for industrial and military applications. The 700 is still operational at several British nuclear power stations in 2010 in control and data processing applications. It was also used as a production control platform for companies such as Kodak.

M700

The M700 series of computers was based on the architecture and instruction set of the Ferranti Argus 700 computer series. Both M700 computers and Argus 700 computers have a common overall instruction set. However, particular models do not necessarily implement the complete instruction set. M700 included a range of computers which were all based on the same architectural features and instruction set ensuring a high level of compatibility and interchangeability in hardware and software terms. Within these limits there existed different implementations from more than one manufacturer to reflect specific commercial and application requirements.[3]

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